The invention relates to flash memory, and more specifically, to an apparatus and method for accessing page mode flash memory.
Currently, typical standard flash memory operates with random access times of about 70-90 ns. Please refer to FIG. 1. FIG. 1 is a table comparing access times for page mode flash memory and standard flash memory. When accessing a byte or word of data in standard flash memory, the time required for accessing each byte is the same. In FIG. 1, the access time tACC for each byte of standard flash is 90 ns. Even when accessing multiple bytes of memory in the same page of the standard flash memory, the access the access time for each byte of memory still remains the same.
To enhance the performance of flash memory, some flash manufactures, such as AMD®, have come up with an approach called page mode flash memory. Unlike standard flash memory having the same access times for every byte or word, page mode flash offers reduced access times when accessing multiple bytes or words within the same page of memory. As shown in FIG. 1, the access time tACC required for reading the first byte in a page of memory is comparable to the amount of time required in standard flash. However, when accessing other bytes in the same page of the page mode flash memory, the access time tPACC is significantly lower than the access time tACC for the first byte of memory.
Please refer to FIG. 2. FIG. 2 is a block diagram of a conventional flash memory access system 10. The system 10 contains a microprocessor 12 connected to a standard flash memory 16. Traditional microprocessors do not support different access times, and therefore they cannot take advantage of page mode flash. As an example, the microprocessor 12 shown in FIG. 2 is the Intel® 8032 microprocessor. The microprocessor 12 sends address information to a latch 14 and sends address and data information to the flash memory 16. The microprocessor 12 outputs an address latch enable single ALE for latching the address in the latch 14, and outputs a program strobe enable signal PSEN for reading data from the flash memory 16.
Please refer to FIG. 3. FIG. 3 shows a timing diagram of the flash memory access system 10 reading from standard flash memory 16. Multiple addresses Aa, Ab, and Ac corresponding to bytes of the same page of the flash memory 16 are accessed, but the access times tACC are the same for each byte of data accessed by the microprocessor 12. Even if the standard flash memory 16 is replaced with page mode flash memory, the microprocessor 12 of the conventional flash memory access system 10 is unable to adjust the access times used for accessing multiple bytes of data within the same page of memory.